1. Field of the Invention
The present invention relates to an image display device which performs a display control of pixels using thin film transistors (TFT).
2. Description of the Related Art
Among image display devices such as a liquid crystal display device and an organic EL (Electro Luminescence) display device, for example, there has been known an image display device which performs a display control of each pixel by an active matrix method which uses a thin film transistor (see JP-A-2003-5709 (patent document 1) and JP-A-2003-122301 (patent document 2), for example). In such an image display device, the pixels are arranged in a matrix array, one scanning signal line is arranged for every pixel row of the pixel matrix, and one data signal line (image signal line) is arranged for every pixel column. Further, a pixel circuit which performs a display control of the pixel is arranged in each pixel. The pixel circuit includes at least one thin film transistor, the pixel circuit is connected to the scanning signal line via a gate electrode of the thin film transistor, and the pixel circuit is connected to the data signal line via either one of a source electrode and a drain electrode of the thin film transistor. In such an image display device, an ON/OFF operation of the thin film transistor is controlled by applying voltages to the scanning signal line and the data signal line corresponding to the pixel which is subject to a display control thus performing a display control of the pixel.
Here, one example of a pixel control in an organic EL display device of the related art is explained. FIG. 11 is a view showing one example of the schematic constitution of circuits formed on a substrate of the organic EL display device of the related art. FIG. 12 is a schematic view showing one example of signals inputted into a scanning signal line SEL, a reset signal line RES and a data signal line DTL. In FIG. 12, signals which are inputted into the respective signal lines during three horizontal periods H(n), H(n+1) and H(n+2) are shown. Symbol SEL(n) indicates the scanning signal lines SEL corresponding to the nth pixel row PLI counted from a signal drive circuit DDR side, and symbol RES(n) indicates a reset signal line RES corresponding to the nth pixel row PLI counted from the signal drive circuit DDR side. Assume that both a thin film transistor T1 whose ON/OFF operation is controlled by the scanning signal line SEL and a thin film transistor T2 whose ON/OFF operation is controlled by the reset signal line RES have the p-type channel structure. Accordingly, a high voltage of the scanning signal lines SEL and a high voltage of the reset signal line RES correspond to an OFF state of the thin film transistor T1 and an OFF state of the thin film transistor T2 respectively, while a low voltage of the scanning signal line SEL and a low voltage of the reset signal line RES correspond to an ON state of the thin film transistor T1 and an ON state of the thin film transistor T2 respectively.
The display control of the nth pixel row PLI is executed during the horizontal period H(n). To be more specific, first of all, the thin film transistors T1, T2 of the nth pixel row PLI are set to an ON state (Tx). Here, a reference voltage is applied to one side of a first pixel capacitor C1 from the data signal line DTL via the thin film transistor T1, and a reset voltage corresponding to a characteristic of a thin film transistor T3 and a characteristic of an organic light emitting diode element OLED is applied to an opposite side of the first pixel capacitor C1 and these voltages are stored in the first pixel capacitor C1. Here, irregularities of the thin film transistor T3 of each pixel are canceled. Thereafter, the thin film transistor T2 returns to an OFF state (Ty), a data signal voltage is applied to the data signal line DTL, and a differential between the reference voltage and the data signal voltage is applied to a gate of the thin film transistor T3 via the thin film transistor T1 in an ON state and the first pixel capacitor C1. An electric current which flows into the pixel is decided in accordance with the voltage applied to the gate of the thin film transistor T3, and the organic light emitting diode element OLED starts emission of light correspondingly to the electric current. Then, at timing at which the horizontal period H(n) is finished, the thin film transistor T1 returns to an OFF state (Tz). Here, the data signal voltage written in the pixel is continuously held in the second pixel capacitor C2 even after the thin film transistor T1 assumes an OFF state and hence, the organic light emitting diode element OLED continues emission of light with brightness corresponding to the data signal voltage written in the pixel. In the same manner, a display control of the (n+1)th pixel row PLI is executed during the next horizontal period H (n+1), and a display control of the (n+2) th pixel row PLI is executed during the next horizontal period H(n+2).
With respect to the organic EL display device, there may be a case where a display control of each pixel is performed such that 1 frame period ( 1/60 sec, for example) is divided into a writing period for writing a data signal voltage into each pixel (pixel circuit) and a light emission period for allowing each pixel to emit light (see patent document 2, for example)